How do I enable the Avalon override in RTL simulation for PHY Lite for Parallel Interfaces Intel® Agilex™ 7 FPGA IP ? - How do I enable the Avalon override in RTL simulation for PHY Lite for Parallel Interfaces Intel® Agilex™ 7 FPGA IP ? Description Due to a problem in Quartus® Prime Pro Edition Software version 22.4, the RTL simulation with Dynamic Reconfiguration will not perform writing to the Avalon® Memory Mapped interface because it is disabled by default. Resolution To work around this problem in Quartus® Prime Pro Edition Software version 22.4, write 32'b1 to the byte control register address to enable the Avalon* override. In the PHYlite example design with Dynamic Reconfiguration, this step is performed as the IOSSM_INIT_WRITE state in the test_logic_iossm module of the tester IP. Additional Information This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 23.1. Custom Fields values: ['novalue'] Troubleshooting 22016251172 False ['PHY Lite for Parallel Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']