ChaCha20-Poly1305 IP core - ChaCha20-Poly1305 IP core implements the ChaCha20 stream cipher together with the Poly1305 message authentication code (MAC), following the IETF standard for Authenticated Encryption with Associated… At Design Gateway, we specialize in developing application-specific FPGA IP cores that empower mission-critical systems across industries such as aerospace, automotive, finance, medical, industrial… Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Arria® 10 SX FPGA ChaCha20 provides high-speed encryption and decryption with strong resistance against timing attacks, while Poly1305 ensures message authentication and integrity. Together, they form a widely adopted AEAD construction. The core supports a 256-bit key size and a 96-bit IV size. It also supports zero-length Additional Authenticated Data (AAD) or plaintext input, making it flexible for a wide range of secure applications. Networking / Security Aerospace Consumer Defense Government Medical Test Transportation ChaCha20-Poly1305 IP core Key Features Fully compliant with ChaCha20Poly1305 AEAD standard (RFC 8439) Offering Brief No No No No VHDL Agilex™ 5 FPGA E-Series Agilex™ 7 FPGA F-Series Arria® 10 SX FPGA No No 24.3.1 Offering Brief Development a1JUi000009IxpFMAS What's Included Encrypted IP core Ordering Information NET-ChaCha20Poly1305-IP a1JUi000009IxpFMAS Development Intellectual Property (IP) a1MUi00000BO8rfMAD a1MUi00000BO8rfMAD Select 2026-07-17T22:06:19.000+0000 ChaCha20-Poly1305 IP core implements the ChaCha20 stream cipher together with the Poly1305 message authentication code (MAC), following the IETF standard for Authenticated Encryption with Associated Data (AEAD). Partner Solutions