Why can’t I generate 2 or 3 channel E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP when "1 to 4 10GE/25GE with optional RSFEC" or "100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP" core variant are selected and "Enable AN/LT" is enabled? - Why can’t I generate 2 or 3 channel E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP when "1 to 4 10GE/25GE with optional RSFEC" or "100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP" core variant are selected and "Enable AN/LT" is enabled? Description Due to a problem in the Intel® Quartus® Prime software version 19.1, the number of channels that are allowed to be created when using the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP when " 1 to 4 10GE/25GE with optional RSFEC " or " 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP " core variant are selected and " Enable AN/LT " is enabled, is incorrectly limited to just 1 or 4 channel configurations. Resolution This problem has been fixed starting in the 19.2 release of the Intel® Quartus® Prime software. Up to (4) channels will then be allowed for these configurations of the IP when " Enable AN/LT " has been selected. Custom Fields values: ['novalue'] Troubleshooting 1806999958, 1409016256 True ['E-tile Hard IP for Ethernet IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 19.2 19.1 ['Agilex™ 7 FPGA F-Series', 'Stratix® 10 MX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']