Are there any restrictions for which reference clock source should be used for the CMU PLL on Arria V GT devices when running at data rates > 6.5536Gbps? - Are there any restrictions for which reference clock source should be used for the CMU PLL on Arria V GT devices when running at data rates > 6.5536Gbps? Description Yes, as shown in Table 2-1 of the Transceiver Clocking section of the Arria® V Handbook, when using the CMU PLL at data rates > 6.5536 Gbps on Arria V GT devices, the dedicated reference clock pin within the same triplet as the intended CMU PLL resides should be used as the reference clock source. The Quartus® II software will allow you to compile the design when an alternative reference clock is sourced from the reference clock network, but this is non-optimal. The dedicated reference clock pin of the triplet must be used for optimal jitter performance. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA'] ['novalue'] ['novalue'] ['novalue']