Reset Methodology - Same Course in Japanese: リセットの方法 19 Minutes In this course, you will learn reset design techniques that you can use to achieve reliable power-up and reset release conditions along with maximum performance on Altera® Hyperflex™ FPGA architecture devices. The main purpose in providing a reset to your design is to provide stability and to prevent power-on to an unknown state. However, improper reset implementation can cause functional errors. Improper reset implementation can also cause restrictions during the Fitter’s Retime Stage. These restrictions can limit the register movement that balances propagation delays between registers in a chain to shorten critical paths and increase frequency of operation. Course Objectives At course completion, you will be able to: You will be able to have a better understanding on the reset needs of your design and whether you will need to redesign your reset tree. Skills Required Familiarity with Altera® Quartus Prime Pro software Familiarity with HDL simulation If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ORESMODHYPFLX. FPGA_ORESMODHYPFLX. <p>Reset Methodology</p>