Why does derive_pll_clocks fail to automatically constrain PLL output clocks? - Why does derive_pll_clocks fail to automatically constrain PLL output clocks? Description Due to a problem in the Quartus® II software, the Synopsys Design Constraint (SDC) command derive_pll_clocks may not properly constrain phase-locked loop (PLL) outputs. This problem occurs when your design uses PLL clock switchover in 28 nm devices, including Stratix® V, Arria® V, and Cyclone® V devices. Because of this problem, the derive_pll_clocks command does not automatically create the generated clocks on PLL outputs relative to each reference clock input. Resolution To work around this problem, constrain the PLL outputs manually using create_generated_clock SDC commands. Refer to the Related Articles section for more details. This problem is fixed starting with the Intel® Quartus® Prime Pro or Standard Edition Software version 11.0. Related Articles Why does my PLL output have an incorrect phase shift in the TimeQuest timing analyzer? How do I constrain PLL clocks when using clock switchover in 28 nm devices? Custom Fields values: ['novalue'] Troubleshooting 2205969500 False ['PLL'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']