Why is there no TX output when simulating the IrDA UART IP? - Why is there no TX output when simulating the IrDA UART IP? Description Due to a problem in IrDA UART simulation model in the Quartus® Prime software version 15.1 and earlier, data is not loaded from the FIFO to the IrDA TX output. Resolution This problem has been fixed beginning with the Quartus Prime Standard edition software version 16.0 Update. Custom Fields values: ['novalue'] Troubleshooting FB: 412121; False ['IrDA UART IP'] ['FPGA Dev Tools Quartus® Prime Software Standard'] 16.0.2 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']