Does Altera provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI? - Does Altera provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI? Description Altera® does not provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI. You can refer to the Input Signal Edge Rate Guidance (PDF) White Paper for further guidance on this topic. Related Articles What is the rise and fall time requirement for the JTAG data (TDO) going to the USB Blaster? What are the recommended rise and fall time specifications for Altera® devices? Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® GX FPGA', 'Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® FPGAs', 'Cyclone® II FPGAs', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'HardCopy™ III ASIC Devices', 'HardCopy™ IV E ASIC Devices', 'HardCopy™ IV GX ASIC Devices', 'MAX® II CPLDs', 'MAX® II Z CPLD', 'MAX® V CPLDs', 'Stratix® FPGAs', 'Stratix® GX FPGA', 'Stratix® II FPGAs', 'Stratix® II GX FPGA', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']