Simulation of 10GBASE-R, Custom, Interlaken, Low Latency, PCI Express PIPE, and XAUI Transceiver PHY IP Cores Fails for Stratix V if You Use ModelSim With Mixed Languages - Simulation of 10GBASE-R, Custom, Interlaken, Low Latency, PCI Express PIPE, and XAUI Transceiver PHY IP Cores Fails for Stratix V if You Use ModelSim With Mixed Languages Description Simulation of 10GBASE-R, Custom, Interlaken, Low Latency, PCI Express PIPE, and XAUI Transceiver PHY IP cores for Stratix V devices fails if you use ModelSim with mixed languages. Resolution Turn off ModelSim optimization with the -novpt option of the vsim command.. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 10.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']