Why is Xcelium* (VHDL and Verilog) simulation failing for the F-tile Dynamic Reconfiguration Suite IP designs? - Why is Xcelium* (VHDL and Verilog) simulation failing for the F-tile Dynamic Reconfiguration Suite IP designs? Description Due to a problem in the Quartus® Prime Pro Edition software version 24.3, you may see Xcelium* (VHDL and Verilog) simulation failure with error “always_ff process requires one and only one event control” for the F-tile Dynamic Reconfiguration Suite Intel FPGA IP designs with the following configurations: ) Ethernet 25G RS-FEC with PTP, ) 100G RS-FEC with PTP, ) 400G RS-FEC with PTP ) Ethernet to CPRI supported PTP version 25G-1 RS-FEC with PTP Resolution This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3.1. Custom Fields values: ['novalue'] Errata 14024372189, 14023416818 False ['F-Tile Dynamic Reconfiguration Suite IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3.1 24.3 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']