Stratix V Hard IP for PCI Express Root Port Includes Unsupported Interrupt Signals - Stratix V Hard IP for PCI Express Root Port Includes Unsupported Interrupt Signals Description The top-level HDL file for the Stratix V Hard IP for PCI Express Root Port includes the following unsupported signals: aer_msi_num, pex_msi_num, app_msi_req, app_msi_ack, app_msi_tc[2:0], and app_msi_num[4:0]. However, these signals are not available for Root Ports. Resolution This issue is fixed in version 11.1 SP2 of the Stratix V Hard IP for PCI Express IP core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1.2 10.1 ['Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']