Why does the GTS Serial Lite IV FPGA IP Design with 16 Gbps PMA data rate fail simulation when the PMA reference clock frequency is set to 160 MHz? - Why does the GTS Serial Lite IV FPGA IP Design with 16 Gbps PMA data rate fail simulation when the PMA reference clock frequency is set to 160 MHz? Description Due to a problem in the Quartus® Prime Pro Edition Software version 24.2, you might observe the GTS Serial Lite IV FPGA IP Design fails simulation while passing the hardware testing for the following configurations: PMA data rate: 16 Gbps PMA reference clock frequency: 160 MHz Resolution To work around this problem, you can choose a different reference clock frequency, for example: {100, 125, 200, 240, 250, 300, 320, 375} MHz. This problem is fixed beginning with the Quartus® Prime Pro Edition software version 24.3 Custom Fields values: ['novalue'] Troubleshooting 15016070201 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.3 24.2 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']