Why does the GTS JESD204B IP Design Example in Dual Simplex PHY only mode remain in the reset state when simulating with the VCSMX simulation tool? - Why does the GTS JESD204B IP Design Example in Dual Simplex PHY only mode remain in the reset state when simulating with the VCSMX simulation tool? Description Due to a problem in the 24.3.1 release of the Quartus® Prime Pro Edition software, the tx_out_of_reset output port is unconnected in the GTS JESD204B IP Design Example in Dual Simplex PHY only mode. This error causes the system to be unable to release both the link reset and frame reset. As the IP is in reset, the IP simulation fails to start. Resolution To work around this problem in version 24.3.1 of the Quartus® Prime Pro Edition software, connect u_jesd_gts_ed_qsys_RX_TX|jesd_gts_ss_rx_tx|ds_group_jesd204b|tx_phy_ds_group_0_inst0_auto_jesd204_tx_out_of_reset (export output port to top level) to wire named tx_out_of_reset[0] in top level wrapper ( intel_jesd204b_gts_ed_RX_TX.sv ) Additionally, Altera recommends installing the following patch in the Quartus® Prime Pro Edition Software version 24.3.1: Download patch 1.20 for Windows (quartus-24.3.1-1.20-windows.exe) Download patch 1.20 for Linux (quartus-24.3.1-1.20-linux.run) Download the Readme for patch 1.20 (quartus-24.3.1-1.20-readme.txt) After installing the patch, regenerate the GTS JESD204B IP Design Example and run the simulation. This problem is fixed in version 25.1 of the Quartus® Prime Pro Edition Software. Custom Fields values: ['novalue'] Troubleshooting 15017172309 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.1 24.3.1 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']