Why do I see timing violations for the altera_reserved_tck signal when using DDR3 SDRAM controller with UniPHY? - Why do I see timing violations for the altera_reserved_tck signal when using DDR3 SDRAM controller with UniPHY? Description Due to a problem in the Quartus® II software version 12.1sp1 and before, when instantiating a DDR3 SDRAM controller with UniPHY, you may get a hold timing violation for altera_reserved_tck . The reason for this violation is that the Quartus II software doesn't recognize the JTAG output as a clock. Resolution To work around this violation, assign the clock to a clock network using the following Quartus settings file (.qsf) assignment: set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to "altera_internal_jtag~TCKUTAP". This issue has been fixed beginning with the Quartus II software version 13.0. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.0 12.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']