Quartus® Prime Software Hyper-Aware Design Flow - 24 Minutes In the Quartus® Prime Software Hyper-Aware Design Flow course, you will learn about two Quartus Prime Pro software features, the Hyper-Retimer and Hyper-Aware CAD. Together these two features enable your designs to take full advantage of Hyper-Registers found in the Hyperflex™ architecture. You will then learn how you can further improve your clock speeds by analyzing retiming reports produced during compilation. Lastly, you will see how existing Quartus Prime Pro software tools have also been modified to support the understanding of Hyper-Register use. Course Objectives At course completion, you will be able to: Use the Hyper-Retimer module to improve compilation results in Altera® FPGAs with the Hyperflex architecture Describe how Hyper-aware CAD settings can be used to improve the effectiveness of your FPGA’s placement and routing use Quartus Prime software tools to Analyze and improve Retiming results Use Quartus Prime software tools to Analyze and improve Retiming results Skills Required Familiarity with FPGA/CPLD design flow Familiarity with the Altera® Quartus Prime Pro design software If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com Reference Course Code: FPGA_OS10TOOLS. FPGA_OS10TOOLS. <p>Quartus Prime Software Hyper-Aware Design Flow</p>