Why do I see errors when compiling the Video Sync Generator in Quartus II 13.0 and 13.0sp1. - Why do I see errors when compiling the Video Sync Generator in Quartus II 13.0 and 13.0sp1. Description Due to a problem in the Quartus® II software version 13.0 and 13.0sp1, the Video Sync Generator component does not declare HDL parameters for Qsys systems generated in Verilog. Resolution To workaround this issue manually remove the 2 lines below in the altera_avalon_video_sync_generator_hw.tcl file, refresh the Qsys systemand regenerate the Qsys system. package require -exact sopc 9.1 set_module_property ANALYZE_HDL "false" This problem is fixed beginning with the Quartus II software version 13.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 13.1 13.0 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']