Warning: <SystemVerilog file>: (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. - Warning: <SystemVerilog file>: (vlog-2186) SystemVerilog testbench feature (randomization, coverage or assertion) detected in the design. These features are only supported in Questasim. Description This warning may appear in the ModelSim-Altera Edition software when there is randomization, coverage, or an assertion in a SystemVerilog file used for simulation. The ModelSim-Altera Edition software does not support randomization, coverage, or assertions. Lines with this feature in your simulation files are ignored. Resolution To work around this problem, use a simulation tool that supports these features, such as QuestaSim or VCS. The simulation results are not affected when these features are used. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']