Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name" - Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name" Description When recompiling the PCI Express® reference design supplied with AN465 the following error occurs: Error: pcie_sv_hip_de_hip_status_0: wrong # args: should be "proc_quartus_synth name" while executing "proc_quartus_synth" (procedure "proc_sim_verilog" line 2) invoked from within "proc_sim_verilog altpcie_sv_hip_ast_hip_status_bridge"? This error relates to the gasket Application Layer logic that drives LEDs on the PCB. It is not required when creating a full PCIe design. You may remove the Qsys element and have no loss of functionality. Resolution Remove Qsys component pcie_sv_hip_de_hip_status_0. Related Articles Error: pcie_av_hip_de_hip_status_0: wrong # args: should be proc_quartus_synth name Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']