About memory usage, Quartus, MAX10 - About memory usage, Quartus, MAX10 Hello! I have developed a FPGA software (NB: I'm not sure it can be called software, but anyway verilog code), about 2+ years ago. As it needed a sinewave, I used coefficients stored in a double access ROM. 1024 coefficients, 18-bit. This should yield (and I think it did at that time) 18 kbits memory usage. See the following code. Now when compiling that code, the memory usage is 16k (16384 bits to be accurate). Could anybody explain me what's wrong and how to fix it? Best regards, Pascal ------------ DA ROM --------------- // Quartus Prime Verilog Template // Dual Port ROM module sine_rom //#(parameter DATA_WIDTH=`ROM_DATW-1, parameter ADDR_WIDTH=`ROM_ADDW) #(parameter DATA_WIDTH=18, parameter ADDR_WIDTH=10) ( input [(ADDR_WIDTH-1):0] addr_a, addr_b, input clk, output reg signed[(DATA_WIDTH-1):0] q_a, q_b ); // Declare the ROM variable reg signed[DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0]; // 18 * 1024 in this case initial begin $readmemh("SineFiles/sine18_1ks.hex", rom); end always @ (posedge clk) begin q_a <= rom[addr_a]; q_b <= rom[addr_b]; end endmodule ----------------------------------- Replies: Re: About memory usage, Quartus, MAX10 Hello! Thanks for your reply. Indeed, what you describe is right. I wanted to build a complete new version from scratch because of beginner problems in my very first project, beginner that I still am. I oversimplified the project. It used to make a linear interpolation between 2 consecutive samples, caculating in 18 bits, then rendering the result in 16. An for a start, I was using only one of the samples (i.e. no interpolation), therefore the 2 last bits were not used at all. Thanks a lot for your help, it works now, and the compilation reports 18432 bits used, which is exactly 18 * 1024. The numbers match, now. Pascal Replies: Re: About memory usage, Quartus, MAX10 Can't be answered without seeing the complete design. Most likely two bits are redundant (not driving actual logic).