Why does the LPM_ADD_SUB IP core generate incorrect results? - Why does the LPM_ADD_SUB IP core generate incorrect results? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software, you might get incorrect results in hardware when using the LPM_ADD_SUB IP core for Intel® Stratix® 10 devices. The problem occurs only when a pipeline stage of greater than 1 is used. The simulation yields correct results. Resolution To work around the problem, use the pipeline stage of 1 or 0. Custom Fields values: ['novalue'] Troubleshooting FB: 533370; False ['Generic Component'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.0 17.1.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']