When executing the KEY_VERIFY instruction, why are register bits related to the volatile key sometimes set after power-up, even though no key is programmed in Stratix V, Arria V or Cyclone V devices? - When executing the KEY_VERIFY instruction, why are register bits related to the volatile key sometimes set after power-up, even though no key is programmed in Stratix V, Arria V or Cyclone V devices? Description You may observe register bits related to the volatile key sometimes being set after power-up when executing the KEY_VERIFY JTAG instruction, even though no key is programmed in Stratix® V, Arria® V or Cyclone® V devices. This is because there is no power-up reset for the registers that are powered by VCCBAT, so these bits are undefined at power-up. This will not cause an issue with programming the key. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']