Why does the RapidIO II auto-generated VHDL simulation testbench fail to compile in certain configurations of the RapidIO II IP core? - Why does the RapidIO II auto-generated VHDL simulation testbench fail to compile in certain configurations of the RapidIO II IP core? Description In some configurations of the RapidIO® II IP core, generated VHDL simulation will encounter compilation error where a port is missing in the entity instantiating another entity. Example Error in ModelSim® simulator. Port "<port_name>" of entity "<entity name>" is not in the component being instantiated. This error is only found in variations where the I/O Master, I/O Slave, Doorbell, Maintenance or Pass-through modules are disabled. Verilog version is not impacted. Resolution Use Verilog version of the simulation testbench. Custom Fields values: ['novalue'] Troubleshooting FB: 439527; True ['RapidIO II (IDLE2 up to 6.25 Gbaud) IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 17.0 15.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Stratix® 10 FPGAs and SoCs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']