Why does the Stratix 10 Native PHY IP Core for PIPE lane polarity inversion not take effect immediately? - Why does the Stratix 10 Native PHY IP Core for PIPE lane polarity inversion not take effect immediately?
Description When pipe_rx_polarity is asserted to invert the lane polarity, it may take up to 24 PCLKs rather than up to 20 PCLKs in Gen1/2 for the inverted data to appear on the rx_parallel_data bus.
Custom Fields values:
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Troubleshooting
FB: 409260;
False
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['Stratix® 10 FPGAs and SoCs']
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['novalue'] - 2021-08-25
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