Why does the F-Tile JESD204B Agilex™ 7 FPGA IP Design Example Generation fail when the data rate is between 16.3 Gbps and 17.1 Gbps? - Why does the F-Tile JESD204B Agilex™ 7 FPGA IP Design Example Generation fail when the data rate is between 16.3 Gbps and 17.1 Gbps? Description Due to a problem in the Quartus® Prime Pro Edition Software version 22.4 and earlier, you may see the F-Tile JESD204B Agilex™ 7 FPGA IP Design Example Generation failure when the data rate is between 16.3 Gbps and 17.1 Gbps for all PMA speed grade devices. The cause of this problem is an internal phase-locked loop (PLL) is being selected to the incorrect mode. Resolution There is no workaround. Custom Fields values: ['novalue'] Errata 14017841142 False ['JESD204B IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 23.1 22.4 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']