Why is the system PLL incorrectly instantiated for F-tile Ethernet Hard IP 400G-4 FHT design examples with Auto-Negotiation and Link Training (AN/LT) enabled? - Why is the system PLL incorrectly instantiated for F-tile Ethernet Hard IP 400G-4 FHT design examples with Auto-Negotiation and Link Training (AN/LT) enabled? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1, you may see an incorrect system PLL instantiated when using the Dual 400G-4 FHT Design Example for F-tile Ethernet Hard IP with Auto-Negotiation and Link Training (AN/LT) enabled designs. Resolution For a workaround for this problem, follow the steps below: Open the “eth_f_hw.v” file and update the lines below 1) Add the below line: wire [INSTANCE_NUM-1:0] o_refclk_out; 2) In the systemclk_f_0 section, update the commands below: systemclk_f_0 sys_pll( //.out_systempll_synthlock_0(), .out_systempll_clock_0(i_clk_sys[portid2]), //.out_refclk_fgt_1(), .in_refclk_fgt_1(i_refclk2pll[portid2]), .in_refclk_fht_0(i_bk_refclk2pll[portid2]), .out_fht_cmmpll_clk_0(i_clk_ref[portid2]), .out)coreclk_1 (o_refclk_out[portid2]) ); See below highlighted lines below for reference This problem is scheduled to be fixed in a future version of the Quartus® Prime Pro Edition software. Custom Fields values: ['novalue'] Troubleshooting 18042616914 False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 25.1 ['Agilex™ 7 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']