IntxAck_o of the Hard IP for PCI Express with Avalon-MM Interface Is Connected to 1'b0 for Cyclone V and Arria V Devices - IntxAck_o of the Hard IP for PCI Express with Avalon-MM Interface Is Connected to 1'b0 for Cyclone V and Arria V Devices Description IntxAck_o is active in the Legacy Interrupt Assertion and Legacy Interrupt Deassertion timing diagrams found in the Arria V and Cyclone V Avalon-MM Interface for PCIe Solutions User Guides. However, for Arria V and Cyclone V devices, IntxAck_o is not active. Resolution No workaround is necessary. IntxReq_i instructs the Hard IP for PCI Express to send an Assert_INTA message TLP. The deassertion of IntxReq_i instructs the Hard IP for PCI Express to send a Deassert_INTA message. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 15.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']