Why does my fPLL phout port have no output duing simulation using ModelSim? - Why does my fPLL phout port have no output duing simulation using ModelSim? Description Due to a problem in the Quartus® II software version 13.0 and 13.0sp1, you may see that the fPLL DPA output port phout has no valid output during simulation. This problem occurs because the current fPLL simulation model for the DPA output port is not supported. The phout output port is only a required connection in your RTL when using ALTLVDS_RX in external PLL mode. Resolution The issue is scheduled to be fixed in a future release of the Quartus II software. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] novalue 13.0 ['Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Stratix® GX FPGA', 'Stratix® V E FPGA', 'Stratix® V FPGAs', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']