Why is it hung when I poll o_tx_hip_ready for assertion in the GTS CPRI PHY FPGA IP with the Agilex™ 5 device ? - Why is it hung when I poll o_tx_hip_ready for assertion in the GTS CPRI PHY FPGA IP with the Agilex™ 5 device ? Description The o_tx_hip_ready port is exposed in the GTS CPRI PHY FPGA IP but it’s not used. If you poll o_tx_hip_ready port for status check, the assertion will never happen. Resolution This problem is fixed beginning with the Quartus Prime Pro Edition Software version 24.2. Custom Fields values: ['novalue'] Troubleshooting 15015795561 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 24.2 24.1 ['Agilex™ 5 FPGA E-Series'] ['novalue'] ['novalue'] ['novalue']