Why can't encrypted Verilog HDL source code be synthesized? - Why can't encrypted Verilog HDL source code be synthesized? Description Due to a problem in the Quartus® Prime Pro Edition Software version 17.1 and earlier, you may see error messages when you synthesize the encrypted Verilog HDL file. This problem occurs when the file is added in the GUI. Resolution You can work around this problem by adding encrypted files in .qsf (Quartus Settings File) manually shown as below. set_global_assignment -name VERILOG_FILE <file name>.vp Custom Fields values: ['novalue'] Troubleshooting 2205682591 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']