Can I distribute the channels of an Agilex™ 7 FPGA M-Series LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode between two sub-banks? - Can I distribute the channels of an Agilex™ 7 FPGA M-Series LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode between two sub-banks? Description Yes, it is possible to distribute the channels between two sub-banks when using an Agilex™ 7 FPGA M-Series LVDS SERDES IP in RX DPA-FIFO or Soft-CDR mode. The channels need to be distributed across 5 or more bytes to use two sub-banks. The lowest 4 bytes used should be placed in one sub-bank, while the remaining bytes will be placed in the other sub-bank. Resolution When developing the pinout distribution and location of the channels of your Agilex™ 7 FPGA M-Series LVDS SERDES IP in RX DPA-FIFO or Soft-CDR, it is recommended to first validate them using the Interface Planner as well as Quartus® Prime Software Suite. Custom Fields values: ['novalue'] Troubleshooting 14025364837 False ['LVDS SERDES IP'] ['FPGA Dev Tools Quartus® Prime Software'] No plan to fix No plan to fix ['Agilex™ 7 FPGA M-Series'] ['novalue'] ['novalue'] ['novalue']