EtherCAT MASTER IP - NDR has acquired the technology of EtherCAT Hardware Master owned by a major industrial machinery manufacturer, and developed a SoC FPGA IP so that more users can flexibly use it. The FPGA hardware… NDR boasts over 40 years of experience in embedded development, offering established technology essential for industrial systems, including FPGA design, circuit design, and OS porting.The Embedded… Cyclone® V SE SoC FPGA Cyclone® V E FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel® MAX® 10 FPGA Cyclone® V SX SoC FPGA Cyclone® V GX FPGA Cyclone® V ST SoC FPGA Cyclone® V GT FPGA The EtherCAT Master IP is a high-performance IP for SoC FPGAs that significantly reduces software load, allowing more users flexible utilization. The FPGA hardware-based communication engine achieves high-speed communication intervals and stable communication cycles, thus reducing the software load. This enables the allocation of more CPU processing resources to applications, and software load fluctuations (including the addition of functions) do not affect communication. Furthermore, the IP format allows for "direct" integration onto your own board. Ethernet Industrial EtherCAT MASTER IP Key Features High-Speed EtherCAT Master IP, Reduces CPU load and achieves high-precision control. Offering Brief No No No No C/C++ Encrypted VHDL Cyclone® V SE SoC FPGA Cyclone® V E FPGA Intel Agilex® 5 FPGAs and SoC FPGAs E-Series Intel Agilex® 3 FPGAs and SoC FPGAs C-Series Intel® MAX® 10 FPGA Cyclone® V SX SoC FPGA Cyclone® V GX FPGA Cyclone® V ST SoC FPGA Cyclone® V GT FPGA No No 23.1.1 Offering Brief Production a1JUi0000049UKVMA2 What's Included a1JUi0000049UKVMA2 Documentation Ordering Information N-EMB-800 a1JUi0000049UKVMA2 Production Intellectual Property (IP) a1MUi00000BO8slMAD a1MUi00000BO8slMAD Select 2025-12-06T01:09:14.000+0000 NDR has acquired the technology of EtherCAT Hardware Master owned by a major industrial machinery manufacturer, and developed a SoC FPGA IP so that more users can flexibly use it. The FPGA hardware communication engine reduces the software load by providing a fast communication interval and stable communication cycle. The resources required for CPU processing can be allocated to applications and hence the software load fluctuations (including the addition of functions) will not affect the communication. In addition, it is also possible to mount directly to the proprietary boards using the IP. Partner Solutions