Agilex5 add own IP fails in RiscFree - Agilex5 add own IP fails in RiscFree It seems all attempts to add own IP cores fail when accessed from NIOS-V We did simplesrt possible IP core: module pio ( input wire reset_rst, // reset.reset input wire [3:0] avl_mem_address, // word adressing two address bits less input wire avl_mem_read, // .read output wire [31:0] avl_mem_readdata, // .readdata output wire avl_mem_readdatavalid, // .readdatavalid input wire avl_mem_write, // .write input wire [31:0] avl_mem_writedata, // .writedata input wire [3:0] avl_mem_byteenable, // .byteenable output wire avl_mem_waitrequest, // .waitrequest input wire avl_clock // avl_clock.clk ); assign avl_mem_waitrequest = 1'b0; // we are ready always assign avl_mem_readdatavalid = 1'b1; assign avl_mem_readdata = 32'h12345678; endmodule But this also fails, when we open memory browser to look at the memory range assigned we get: [0x800000] Internal error. Abstract command execution failed: An abstract command is currently being executed. We tried with one 3rd party IP core in VHDL with the same error! So what is happening and what can be the problem? Adding IP cores from Altera catalog works well. Replies: Re: Agilex5 add own IP fails in RiscFree Hi I’m glad that your question has been addressed, I will now transition this thread to community support. If you have a new question, Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’ , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions. Regards Jingyang, Teh Replies: Re: Agilex5 add own IP fails in RiscFree I fixed the problem by removing readdatavalid signals. Now it works in RiscFree. So it was a problem with the IP core. It seems the new version of the tools are very strict about Avalon protocol. Replies: Re: Agilex5 add own IP fails in RiscFree Hi Is it possible if you could share us your Quartus Project to understand better the connection? Regards Jingyang, Teh Replies: Re: Agilex5 add own IP fails in RiscFree A number of things. First of all, are you creating this as a custom component in Platform Designer? How are you connecting it to the processor? All data transfers in Platform Designer must be synchronous using the clock. Doing an "assign" like what you've done, there's nothing for the processor to read.