Why are the values for FS (Full Swing) and LF (Low Frequency) zero when simulating a PCIe Hard IP core for Gen3? - Why are the values for FS (Full Swing) and LF (Low Frequency) zero when simulating a PCIe Hard IP core for Gen3? Description There is an issue with the PCIe® Hard IP simulation models when targeting the Stratix® V and Arria® V GZ device families, where the values for FS and LF are zero for Gen3. Certain bus functional models (BFM) may report an error that FS and LF have values that violate the PCIe specification. Resolution This problem is fixed starting with the Intel® Quartus® Prime Standard Edition Software version 14.0. Custom Fields values: ['novalue'] Troubleshooting 2205755333 False ['Simulation'] ['FPGA Dev Tools Quartus II Software'] 14.0 12.0 ['Arria® V GZ FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']