Why does “rg_overflow” assert when using the 100G Interlaken Intel® FPGA IP on the Intel® Arria®10 devices? - Why does “rg_overflow” assert when using the 100G Interlaken Intel® FPGA IP on the Intel® Arria®10 devices? Description Due to a wrong default parameter setting in the 100G Interlaken Intel® FPGA IP on the Intel® Arria® 10 devices, rg_overflow assert when you connect rx_user_clk to a 300 MHz clock, with 12.5 Gbps data rate. Resolution To work around this problem using the Intel® Quartus® Prime Software, modify the file <instance name>/synth/<instance name>.v as follows: Change from: .FAMILY ("Arria 10"), .RXFIFO_ADDR_WIDTH (12), .NUM_LANES (12), Change to: .FAMILY ("Arria 10"), .RXFIFO_ADDR_WIDTH (13), .NUM_LANES (12), If the IP is regenerated, the modified file changes will be overwritten and must be edited again. Custom Fields values: ['novalue'] Troubleshooting 1508378181 False ['Interlaken - 100G for 28nm and 20nm devices (PRIMARY) IP-ILKN/100G'] ['FPGA Dev Tools Quartus® Prime Software Pro'] novalue 18.1 ['Arria® 10 FPGAs and SoCs', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA'] ['novalue'] ['novalue'] ['novalue']