Why is the output latency of the Status Flags for the DCFIFO IP higher than the latency specified in the SCFIFO and DCFIFO IP Cores User Guide? - Why is the output latency of the Status Flags for the DCFIFO IP higher than the latency specified in the SCFIFO and DCFIFO IP Cores User Guide? Description Due to the cross-clocking nature of the DCFIFO IP, the latency of the Status Flags could be 1 greater than that specified in the SCFIFO and DCFIFO IP Cores User Guide (PDF). Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['novalue'] novalue novalue ['Arria® II GX FPGA', 'Arria® II GZ FPGA', 'Arria® V GT FPGA', 'Arria® V GX FPGA', 'Arria® V GZ FPGA', 'Arria® V ST FPGA', 'Arria® V SX FPGA', 'Cyclone® III FPGAs', 'Cyclone® III LS FPGA', 'Cyclone® IV E FPGA', 'Cyclone® IV GX FPGA', 'Cyclone® V E FPGA', 'Cyclone® V GT FPGA', 'Cyclone® V GX FPGA', 'Cyclone® V SE FPGA', 'Cyclone® V ST FPGA', 'Cyclone® V SX FPGA', 'Arria® 10 GT FPGA', 'Arria® 10 GX FPGA', 'Arria® 10 SX FPGA', 'MAX® 10 10 FPGAs', 'MAX® II CPLDs', 'MAX® V CPLDs', 'Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA', 'Stratix® V E FPGA', 'Stratix® V GS FPGA', 'Stratix® V GT FPGA', 'Stratix® V GX FPGA'] ['novalue'] ['novalue'] ['novalue']