Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_clock_mgr.cpp, Line: 8971 - Internal Error: Sub-system: STA, File: /quartus/tsm/sta/sta_clock_mgr.cpp, Line: 8971 Description Due to a problem in the Quartus® Prime Standard Edition software version 19.1, you may see this error during the synthesis stage of compilation. This internal error occurs when using Synplify Pro* FPGA Synthesis software for synthesis. Resolution To workaround this problem, use this assignment: set_global_assignment -name DISABLE_LEGACY_TIMING_ANALYZER ON Custom Fields values: ['novalue'] Troubleshooting 18011601716 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] No plan to fix 19.1 ['Arria® II FPGAs', 'Arria® V FPGAs and SoCs', 'Cyclone® IV FPGAs', 'Cyclone® V FPGAs and SoCs', 'Arria® 10 FPGAs and SoCs', 'Cyclone® 10 LP FPGA', 'MAX® 10 10 FPGAs', 'MAX® II CPLDs', 'MAX® V CPLDs', 'Stratix® IV FPGAs', 'Stratix® V FPGAs'] ['novalue'] ['novalue'] ['novalue']