Why does the Stratix® 10 FPGA External Memory Interfaces DDR4 IP show minimum pulse violations on the wf_clk clocks in the Intel Quartus® Prime timing analyzer? - Why does the Stratix® 10 FPGA External Memory Interfaces DDR4 IP show minimum pulse violations on the wf_clk clocks in the Intel Quartus® Prime timing analyzer? Description Due to a problem in the Quartus® Prime Pro software version 17.1.1, you may see Minimum Pulse Width timing violations associated with the wf_clk_<number> clocks in the Quartus® Compilation TimeQuest report of a project implementing the Stratix® 10 FPGA External Memory Interfaces DDR4 IP. An example of a Minimum Pulse Width timing violation from the Stratix 10® DDR4 example design project is emif_s10_0|emif_s10_0_wf_clk_3 , which has a slack failure of -0.058. Resolution The wf_clk clock minimum pulse width violations can be ignored. This problem is scheduled to be fixed in a future release of the Quartus® Prime Pro software. Custom Fields values: ['novalue'] Troubleshooting FB: 517840; False ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 18.1 17.1.1 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']