Arria V Hard IP for PCI Express Should Return an Error When You Select the 64-Bit Interface for Gen1 x8 or Gen2 x4 Variants - Arria V Hard IP for PCI Express Should Return an Error When You Select the 64-Bit Interface for Gen1 x8 or Gen2 x4 Variants Description You can specify a 64-bit Avalon Streaming (Avalon-ST) interface for the Gen1 x8 and Gen2 x4 Arria V Hard IP for PCI Express IP Cores in both the MegaWizard and Qsys design flows. However, the Gen1 x8 and Gen2 x4 variants require the 128-bit Avalon-ST interface. Resolution This issue is fixed in version 11.1 SP2 of the Arria V Hard IP for PCI Express IP Core. Custom Fields values: ['novalue'] Troubleshooting novalue True ['novalue'] ['FPGA Dev Tools Quartus II Software'] 11.1.2 11.1 ['Arria® V FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']