Why does the AXI read transaction ID (RID) value change during a read data transfer when using the Intel® Stratix® 10 MX HBM2 controller? - Why does the AXI read transaction ID (RID) value change during a read data transfer when using the Intel® Stratix® 10 MX HBM2 controller? Description Due to a problem in the Intel® Stratix® 10 MX HBM2 controller when using the Intel Quartus® Prime Pro Edition software versions 20.4 or earlier, you may see that the AXI master returns a different value for the read address ID axi_0_0_rid signal if the read burst length axi_0_0_arlen signal is greater than 2. Resolution To work around this problem in the Intel® Quartus® Prime Pro Edition software versions 20.4 or earlier, Download hbm_burst_rid_fix.zip file and replace the following encrypted files from the existing ones. ./sim_mentor/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_191/sim/mentor/ ./syn_quartus/altera_axi_ufi_axi_burst_ctrl.sv // Copy to /ip/ed_synth/ed_synth_hbm_0_example_design/altera_axi_ufi_adapter_19 This problem is fixed starting with the Intel® Quartus® Prime Pro Edition software version 21.1. Custom Fields values: ['novalue'] Troubleshooting 1508671216 True ['External Memory Interfaces Stratix® 10 FPGA IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 21.1 20.2 ['Stratix® 10 MX FPGA'] ['novalue'] ['novalue'] ['novalue']