Why does the simulation of the MIPI DSI-2 FPGA IP Design Example fail with default timing parameter settings? - Why does the simulation of the MIPI DSI-2 FPGA IP Design Example fail with default timing parameter settings? Description Due to a problem in the Quartus® Prime Pro Edition software version 25.1.1, users may observe the following error when simulating the MIPI DSI-2 FPGA IP Design Example using the default video timing parameter settings. Fatal: dsi2_ed_sim_tb.dut.dsi2_tx.dsi2_tx.dsi2.mipi_dsi2_tx_inst.<protected>.<protected>: Error: axis_m does not accept back pressure Resolution To work around this problem in the Quartus Prime Pro Edition software version 25.1.1, update the video paramaters as below : Dimension: Default value for HTOTAL: 2176 Default value for VTOTAL: 100 Blank Timing: Default value for HB_END: 2048 Default value for V1B_START: 0 Default value for V1B_END: 4 Syn Timing Default value for HS_START: 52 Default value for HS_END: 100 Default value for V1S_VSTART: 2 Default value for V1S_HSTART: 52 Default value for V1S_VEND: 3 Default value for V1S_HEND: 52 This problem is fixed beginning with the Quartus Prime Pro Edition software version 25.3. Custom Fields values: ['novalue'] Troubleshooting 15018550487 False ['Interfaces'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 25.3 25.1.1 ['Agilex™ 5 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']