ID:20621 3V I/O <text> has <number> enable signals and is locked at pins <text> of the same 3V I/O set. Only two enable signals are allowed. - ID:20621 3V I/O <text> has <number> enable signals and is locked at pins <text> of the same 3V I/O set. Only two enable signals are allowed. Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier for Intel® Stratix® 10 devices, you might see this error message during compilation when only 2 in-out pins are used at 3V I/O bank. This is because the output-only pin in 3V I/O bank of Intel Stratix 10 devices will drive a strong "1" during configuration, the Intel Quartus Prime Pro Edition Software inserts an output-enable (OE) to disable this output until configuration complete. Resolution To work around this problem, do not exceed the OE limit with no more than 2 in-out or output-only pins in total in a 3V I/O bank. This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software. Related Articles Is there a known issue with Intel® Stratix® 10 3V IOs in user mode? Custom Fields values: ['novalue'] Troubleshooting 15011979495 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix 21.2 ['Stratix® 10 FPGAs and SoCs'] ['novalue'] ['novalue'] ['novalue']