Error: enable0 input port of SERDES receiver or transmitter atom "rx_0" must be driven by a clock output port of the fast PLL - Error: enable0 input port of SERDES receiver or transmitter atom "rx_0" must be driven by a clock output port of the fast PLL Description The ALTLVDS_RX megafunction in the Quartus® II software version 10.0 SP1 incorrectly sets the rx_enable pin to std_logic_vector(0 downto 0) in External PLL mode. The corrrect syntax should be std_logic. Resolution A patch is available to fix this problem for the Quartus II software version 10.0 SP1. Download and install Patch 1.114 from the appropriate link below. Download the Quartus II software version 10.0sp1 Patch 1.114 for Windows (.exe) Download the Quartus II software version 10.0sp1 Patch 1.114 for Linux (.tar) Download the Readme for the Quartus II software version 10.0sp1 Patch 1.114 (.txt) This issue is fixed in the Quartus II Software version 10.1. Custom Fields values: ['novalue'] Troubleshooting novalue False ['novalue'] ['FPGA Dev Tools Quartus II Software'] 10.1 novalue ['Stratix® III FPGAs', 'Stratix® IV E FPGA', 'Stratix® IV GT FPGA', 'Stratix® IV GX FPGA'] ['novalue'] ['novalue'] ['novalue']