AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] - AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] Hello, In AGILEX 5E : GTS AXI Streaming IP for PCI Express user guide : ug-813754-855610.pdf What is the mapping of the PCIe Header on "_tuser_hdr[255:0]" signal when the PCIe0/1 AXI-ST Sideband Header parameter is enabled. We have the mapping for the Tdata signal but not for the _tuser_hdr[255:0] signal. Is it the same mapping ? Thank you. Serge Replies: Re: AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] Hi Serge, You are most welcome, if you have any question please do file a new forum thread. We will be there to ensure your success. Regards, Wincent_Altera Replies: Re: AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] Thank you Wincent. Serge Replies: Re: AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] Hi @Serge93 , The header format for inband and sideband is the same, thus we do not have a separate set of definition for sideband header. We will include this information more explicit in our next IP UG version. Regards, Wincent_Altera Replies: Re: AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] Hi , Thanks for your clarification, let me have sometime to check it. Get back to you later. Regards, Wincent_Altera Replies: Re: AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] Hello Wincent, Thank you for your answer but I meant the detail mapping as the following picture for Tdata : Do you have the same for the _tuser_hdr[255:0] signals ? Thank you. Serge Replies: Re: AGILEX 5E : GTS AXI IP PCI Express : What is the mapping of the PCIe Header on _tuser_hdr[255:0] Hi Serge, Based on my understanding, The mapping of the fields in _tuser_hdr is NOT the same as the mapping in tdata. tdata contains the actual TLP data (including header and payload), the _tuser_hdr contains just the header and sideband fields (if I not mistaked), in a format defined by Altera for easier access to header information. The mapping of _tuser_hdr[255:0] is usually ( For real cases, I suggest check the example design or simulation) [127:0] = PCIe TLP Header (DW0-DW3, 32 bits each) [255:128] = Sideband signals or reserved Regards, Wincent