TCPIP-100G: 100G TCP/UDP/IP Hardware Stack - The TCPIP-1G/10G core is a complete hardware TCP/IP stack that supports up to 32k sessions, DHCP, UDP with multicast, and offers configurable low-latency cut-through or reliable store-and-forward… CAST develops, sells, and supports digital Silicon IP Cores which electronic system designers use to shorten development time and lower production risk. CAST uniquely gives system designers the CAST… Agilex™ 9 FPGA Direct RF-Series The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to an Internet Protocol (IP) network and exchange data using the TCP protocol without requiring assistance from — or even the presence of — a system processor. The core acts either as a server or a client and, without assistance from the host system, it autonomously opens, maintains, and closes TCP connections. The system integrating the TCPIP-1G/10G core can configure network parameters and preferences by accessing its control registers, and the core is then able to receive and send data via streaming data interfaces. The highly configurable core can adapt to different applications and diverse system requirements. The maximum number of simultaneous TCP sessions is configurable at synthesis time; it can be as high as 32,768 for devices like data servers, or as small as 1 for edge devices requiring minimum silicon area and power. Further user options include implementing a DHCP client that allows the core to automatically be assigned an IP address, enabling or disabling support of the reassembly of out-of-order TCP packets data, and integrating a UDP hardware stack with multicast support (IGMPv3). Finally, users can choose the packet processing mode, either cut-through or store-and-forward. In cut-through mode, the payload data are delivered to the host system as they arrive without any internal packet buffering and before the packets’ integrity can be validated. As a result, the core operating in cut-through mode features extremely low latency and requires less memory, but it cannot reassemble out-of-order packets and it may deliver data that will subsequently be marked as corrupted. Under the store-and-forward mode of operation, the core will always deliver verified, in-order packets, but will have higher latency and require more memory resources. The TCPIP-1G/10G core is rigorously verified and available in RTL source or as a targeted FPGA netlist. Its deliverables include a testbench, synthesis, and simulation scripts, and comprehensive user documentation. Ethernet Aerospace Data Center Cloud (Public, Private, Hybrid) Defense Industrial Medical Test Transportation TCPIP-100G: 100G TCP/UDP/IP Hardware Stack Key Features 10/100/1000, 2.5G, and 10G Ethernet Transmit and Receive, TCP server or client with up to 32k simultaneous TCP sessions Offering Brief No Yes No No Verilog Agilex™ 9 FPGA Direct RF-Series Yes Yes 24.3.1 Offering Brief Production a1JUi0000049U72MAE What's Included SystemVerilog Source or Targeted Netlist Ordering Information TCPIP-1G/10G a1JUi0000049U72MAE Production Intellectual Property (IP) a1MUi00000BO8rRMAT a1MUi00000BO8rRMAT Member 2026-04-21T12:58:28.000+0000 The TCPIP-1G/10G core is a complete hardware TCP/IP stack that supports up to 32k sessions, DHCP, UDP with multicast, and offers configurable low-latency cut-through or reliable store-and-forward modes. Partner Solutions