Verilog HDL error at <location>: this block requires a name (ID 10644) - Verilog HDL error at <location>: this block requires a name (ID 10644) Description You might see this error message when trying to compile a Verilog HDL Generate Block without a block name defined in the Intel® Quartus® Prime Standard Edition Software. The Intel® Quartus® Prime Pro Edition Software does not have this requirement. Resolution To avoid this error in the Intel® Quartus® Prime Standard Edition Software, name all the blocks used in a generate statement in the Intel® Quartus® Prime Standard Edition Software For example: RTL Code: genvar i; generate for (i = 0; i < N; i = i + 1) begin : <block_name> … end endgenerate Custom Fields values: ['novalue'] Troubleshooting 15010773232 False ['novalue'] ['FPGA Dev Tools Quartus® Prime Software Standard'] novalue 21.1 ['Programmable Logic Devices'] ['novalue'] ['novalue'] ['novalue']