HLS Interfaces (Part 2 of 7) - 31 Minutes In the class, we will cover the various component interfaces that can be generated by the Altera® HLS Compiler. The interfaces covered include scaler interfaces, memory-mapped master and slave interfaces, and streaming interfaces. Course Objectives At course completion, you will be able to: Understand the various interfaces available with the Altera® HLS compiler Select the most optimal interface for various types of components Skills Required Basic understanding of the C++ programming language Basic understanding of FPGAs and the Altera® Quartus Development Environment If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OHLS2. FPGA_OHLS2. <p>HLS Interfaces (Part 2 of 7)</p>