Why am I seeing the error “ZL30733_REG_DPLL_MON_STATUS(1): 0x02 - FAIL, timeout waiting for lock” when running the Multi-Channel 25GbE PTP1588 System Example Design on Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Order code: DK-SI-AGI027FA)? - Why am I seeing the error “ZL30733_REG_DPLL_MON_STATUS(1): 0x02 - FAIL, timeout waiting for lock” when running the Multi-Channel 25GbE PTP1588 System Example Design on Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Order code: DK-SI-AGI027FA)? Description When users run the Multi-Channel 25GbE Time Precision Protocol System Example on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Order code: DK-SI-AGI027FA), the boot log displays the following errors: root@agilex7dksiagi027fc:~# [ 104.167244] ZL30733_REG_DPLL_MON_STATUS(1) : 0x02 - FAIL, timeout waiting for lock [ 104.174844] Switching to OCXO clock [ 104.178545] i2c 1-0070: ZL30733 is not in NCO mode(0x3); set Dpll in NCO mode These errors occur due to termination issues with the ZL30733 clock synthesizer IC on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Order code: DK-SI-AGI027FA). As a result, the required timing accuracy cannot be achieved when running the Multi-Channel 25GbE Time Precision Protocol System Example Design because the ZL30733 DPLL fails to lock. Resolution To ensure proper termination of the ZL30733 clock synthesizer IC on the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (Order code: DK-SI-AGI027FA), users should follow these instructions: Do not populate the following resistors: R814, R815, R803, R804, R801, R802, R816, R817, R805, R806, R818, R819, R440, R924, R152, R926, R153, R943, R738, R945, R775, R827, R784, R785. (Refer to schematic pages 54 and 55 for details.) Populate resistors R800, R807, R809, and R840 with 100 Ohm values. (Refer to schematic page 55 for reference.) Following these steps will help achieve the correct termination for the ZL30733 clock synthesizer IC. Reference snapshots: Schematic Page 54: Schematic Page 55: Board layout snapshots: Custom Fields values: ['novalue'] Troubleshooting NA False ['F-Tile Ethernet Hard IP'] ['FPGA Dev Tools Quartus® Prime Software Pro'] No plan to fix No plan to fix ['Agilex™ 7 FPGA I-Series'] ['novalue'] ['novalue'] ['Agilex™ 7 FPGA I-Series Dev Kit']