Altera® Hyperflex® Architecture Overview - 21 Minutes In the Hyperflex® Architecture Overview, you will learn the new architectural advancements made to FPGAs that enable designs to reach clock speeds not possible with conventional FPGA architectures. You will also receive an overview of the three design techniques for taking full advantage of this architecture, namely Hyper-Retiming, Hyper-Pipelining and Hyper-Optimization. Course Objectives At course completion, you will be able to: Describe the 2nd generation Hyperflex® architecture including: Hyper-Registers and Programmable Clock Tree Synthesis Define Hyper-Retiming, Hyper-Pipelining and Hyper-Optimization, the three techniques for improving design performance in Hyperflex Architectures Skills Required Familiarity with FPGA/CPLD design flow Familiarity with FPGA architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_OS10ARCH. FPGA_OS10ARCH. <p>Altera Hyperflex Architecture overview</p>