Why does the bar size in lspci log not match the configured size in the IP parameter when using Intel® Stratix® 10 H-Tile/L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express*? - Why does the bar size in lspci log not match the configured size in the IP parameter when using Intel® Stratix® 10 H-Tile/L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express*? Description Due to a problem in the Intel® Quartus® Prime Pro Edition Software version 22.2 and earlier, you may see bar size in lspci log doesn't match with the configured size in the IP parameter when using Intel® Stratix® 10 H-Tile/L-Tile Avalon® Memory Mapped (AvalonMM) Hard IP for PCI Express*. Resolution This problem is fixed in Intel® Quartus® Prime Pro Edition Software version 22.2 and onwards. Custom Fields values: ['novalue'] Troubleshooting 18020355308 False ['Avalon-MM Stratix® 10 Hard IP for PCI Express'] ['FPGA Dev Tools Quartus® Prime Software Pro'] 22.2 19.4 ['Stratix® 10 GX FPGA', 'Stratix® 10 MX FPGA', 'Stratix® 10 SX FPGA', 'Stratix® 10 TX FPGA'] ['novalue'] ['novalue'] ['novalue']