Hyperflex® Architecture Design: Pre-Computation - 29 Minutes In FPGAs containing the Altera® Hyperflex® architecture, maximizing performance may require optimizing loops that have become bottlenecks for your design performance. In the Hyperflex Architecture Design: Pre-Computation course, you will discover a strategy that you can employ when this situation happens called pre-computation. This course will help you understand the pre-computation process. Then you will learn two ways in which to use it in your FPGA design: by removing work from the feedback loop and by reducing the loop’s signal dependency. This training applies to all Agilex™ series and Stratix® 10 FPGAs. Course Objectives At course completion, you will be able to: Learn the loop restructuring technique of moving logic from feedback to feedforward Reduce loop size to lessen the impact on Hyper-Retiming Skills Required Familiarity with FPGA/CPLD design flow Familiarity with Verilog or VHDL synthesizable design structures Familiarity with the Quartus Prime Pro development software including Hyper-Retiming and Fast Forward analysis Understanding of the Hyperflex architecture If the audio for the course does not start automatically, press pause and then play on the course player. The transcript of the course audio is available in the Notes or closed captioning (CC) feature of the player. If you need assistance with this course, please email fpgatraining@altera.com . Reference Course Code: FPGA_ OHYPPRECOMP. FPGA_OHYPPRECOMP. <p>Altera Hyperflex FPGA Architecture Design: Pre-Computation</p>